A computer system architecture may be defined as a set of properties that determine what programs will run on the system and what results the programs will produce. The "organization" of a computer system refers generally to the dataflow and control layout within the system. The organization of a computer system is also often referred to as an "implementation" of the system. FIG. 1 illustrates an organization of a conventional computer system 10. The computer system 10 includes a memory 12, a data bus 14, an address bus 16, a number of execution units, and a number of register files. The execution units include an address generator 18, a load/store unit 20, an arithmetic unit 22 and a branch unit 24. The register files include a common 32.times.32 register file 26 shared by the execution units 20, 22 and 24, as well as a base register file 28 and an offset/displacement register file 30 for use in addressing the memory 12 via address generator 18. Control flow in the system 10 assumes that instructions are fetched from memory 12 via a fetch unit 32 and then decoded in a decoder 34 to produce corresponding execution controls. The execution controls then control the flow of data through the execution units. A typical instruction stream in the computer system 10 is shown in Program 1 below:
______________________________________ label: add r3, r1, r2; load r4, base0, offset0; mpy r7, r5, r6; store r7, base1, offset1; branch some.sub.-- label; Program 1: Typical Instruction Stream ______________________________________
The first instruction in Program 1 resides at the symbolic memory address label. The instruction contained at that address instructs the system to add the contents of register r1 in the register file 26 to the contents of register r2 and place the result in register r3. Similarly, the load instruction tells the system to add the contents of base0 in base registers 28 and offset0 in offset/displacement registers 30 to form the effective memory address. The contents of the memory 12 at that address are then placed in register r4 in the register file 26. The multiplication instruction mpy multiplies the contents of registers r5 and r6 and places the result in register r7. The store instruction writes the value of register r7 to the effective memory address formed by adding the contents of base1 and offset1. The branch instruction causes a change in the control flow, such that an instruction address register (IAR) in system 10 will be modified to point to the address some.sub.-- label. Program execution then continues from the modified instruction address.
The above-described conventional computer system organization typically supports a single architecture or "machine view." One known technique for allowing a system such as system 10 to support two machine views involves the use of a branch-exchange instruction to pass control from one processor to another within the system. The branch-exchange instruction invokes an interrupt on a requesting processor to pass control to the other processor, and control returns back to the requesting processor by a similar mechanism. However, this technique generally does not allow any sharing of dataflow execution units. A related technique which does allow some sharing of execution units has been used in the Delft-Java processor to branch between a Java Virtual Machine view and a RISC-based machine view, as described in greater detail in C. J. Glossner and S. Vassiliadis, "The Delft-Java Engine: An Introduction," Lecture Notes in Computer Science, Springer-Verlag, Third International Euro-Par Conference (Euro-Par '97 Parallel Processing), pp. 766-770, Passua, Germany, Aug. 26-29, 1997, which is incorporated by reference herein. In the Delft-Java processor, a reserved opcode is used as a branch-exchange instruction to allow control to be passed back and forth between the two views. Another dual machine view technique is implemented in the ARM Thumb processor, as described in ARM 7TDMI Datasheet, Advanced RISC Machines, Ltd., UK, Document No. ARM DDI 0029E, August 1995. However, in this technique one of the processor machine views is actually an architectural subset of the other machine view.
As previously noted, conventional computer systems are generally unable to support more than two different machine views. Moreover, even those systems which can simultaneously support dual machine views generally cannot be dynamically reprogrammed to support a variety of different types of machine views using, for example, field programmable gate arrays (FPGAs) or other reconfigurable hardware. The total number and type of machine views which can be supported in a given conventional system is therefore unduly limited, as is the degree to which execution units and other processing elements can be shared between machine views.